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🧠 Understanding Object Memory Sharing in SystemVerilog

📘 Introduction

In SystemVerilog, when you assign one object to another (e.g., tr2 = tr1;), you are not creating a copy of the object, but instead making tr2 refer to the same memory location as tr1. In this post, we'll demonstrate how object handles work and how changing one affects the other.

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🧱 Object Handle vs Object Instance

• An object handle is just a reference (or pointer) to the memory location of an actual object.

• When you assign tr2 = tr1;, both handles point to the same memory.

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🔧 Example Code: Shared Object Memory

class example;
  bit [3:0] a;
endclass
module sample;
  example tr1, tr2;
  initial begin
    tr1 = new();              // Allocate memory
    tr1.a = $random;          // Random value assigned to tr1.a
    tr2 = tr1;                // tr2 now refers to same object as tr1
    $display("Initial: tr1.a = %0b", tr1.a);
    $display("Initial: tr2.a = %0b", tr2.a);
    tr2.a = $random;          // Modify value using tr2
    $display("After change:");
    $display("tr1.a = %0b", tr1.a);
    $display("tr2.a = %0b", tr2.a);
  end
endmodule
Expected Output:
Initial: tr1.a = 1101
Initial: tr2.a = 1101
After change:
tr1.a = 0011
tr2.a = 0011
🧵 What’s Happening Behind the Scenes?
tr1 = new(); allocates memory for an object of class example.
tr2 = tr1; makes both tr1 and tr2 point to the same memory.
Changing tr2.a also affects tr1.a, since it's the same object.

📌 Takeaway
SystemVerilog object handles behave like pointers in C/C++.
To create a true copy (deep copy), you must write a method that creates a new object and copies the values manually.