Loop Control Statements in System Verilog

Title: SystemVerilog Control Flow Constructs with Arrays and Loops

Introduction

In SystemVerilog, control flow constructs such as repeat, foreach, for, while, and forever are essential to write efficient and readable simulation code. These loops allow us to traverse arrays, execute code multiple times, and control the execution flow with keywords like continue and break.

In this post, we explore how these loops work using practical examples with queues and multidimensional arrays.

Code Example:

module example;

int i, j, l, m;

int arr[$] = '{3, 4, 5, 6, 7, 8}; // Queue

int mul_dim[5][3];

int array[5];

initial begin

$display("-------repeat with array-----");

repeat($size(array)) begin

array[m] = m;

$display("value of array[%0d] = %0d", m, array[m]);

m++;

end

$display("--------repeat----------");

repeat(5) begin

$display("value of l = %0d", l);

l++;

end

$display("----foreach with multidimensional array----");

foreach (mul_dim[i, j])

$display("value of mul_dim[%0d][%0d] = %0d", i, j, $urandom_range(1, 300));

$display("----------foreach loop over queue------");

foreach (arr[i])

$display("array[%0d] = %0d", i, arr[i]);

$display("---------for loop----------");

for (int k = 0; k < 8; k++) begin

if (k == 2)

continue;

$display("value of k = %0d", k);

end

$display("------while loop----------");

while (j < 8) begin

if (j == 6)

break;

$display("value of j = %0d", j);

j++;

end

$display("------forever loop----------");

forever begin

$display("value of i = %0d", i);

#0.5;

i++;

end

initial begin

#10;

$finish;

end

endmodule

Explanation

1. `repeat` Loop

Used to execute a block of code a specific number of times. It's useful for fixed iterations like initializing arrays.

2. `foreach` Loop

Iterates through each element of an array. It's ideal for queues, arrays, and multidimensional arrays.

3. `for` Loop

A classic loop structure for controlled iteration. continue is used to skip a specific iteration, and break to exit early.

4. `while` Loop

Executes as long as the condition is true. Perfect when the number of iterations is unknown beforehand.

5. `forever` Loop

Executes an infinite loop. Typically used in simulation to create continuous behavior until manually stopped or broken.

Output Highlights

Arrays are initialized and displayed using repeat.
Random values are generated for a 2D array using foreach.
continue skips index 2 in a for loop.
break exits the loop once j equals 6 in the while loop.
The forever loop continuously displays the value of i until simulation ends.

Conclusion

SystemVerilog provides a rich set of loop constructs that make code concise and powerful, especially when working with complex arrays and simulation flow. Mastering these constructs helps in writing robust testbenches and simulations.

Ticker