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🔄 Flip-Flops in Digital Electronics: JK, D, T & SR Flip-Flops Using SystemVerilog
📘 Introduction: What Is a Flip-Flop?
Have you ever wondered how a processor remembers a bit of data, how a counter keeps track of numbers, or how digital circuits store information?
The answer begins with flip-flops!
A flip-flop is a sequential digital circuit that stores one bit of information — either "0" or "1". Unlike a combinational circuit, whose output depends only on its current inputs, a flip-flop generally updates its output in response to a clock edge.
Flip-flops are essential components in:
- CPU registers and data storage.
- Counters and frequency dividers.
- Finite State Machines (FSMs).
- Shift registers and pipeline registers.
- Synchronization and control circuits.
In this tutorial, we will explore four important flip-flops using SystemVerilog:
1. D Flip-Flop — Data storage.
2. JK Flip-Flop — Set, reset, hold and toggle.
3. T Flip-Flop — Toggle operation.
4. SR Flip-Flop — Set and reset control.
For each type, we will understand its operation, truth table, SystemVerilog implementation, and practical applications.
⏰ 1. Understanding the Clock Signal
A clock is a periodic signal that synchronizes sequential circuits.
A rising edge occurs when the clock changes from "0" to "1". In SystemVerilog, "posedge clk" represents this transition.
always @(posedge clk) begin
// Update the stored value
end
The output of a positive-edge-triggered flip-flop updates at the rising edge, not continuously whenever an input changes.
Remember: "<=" is the nonblocking assignment operator commonly used for sequential RTL.
🧷 2. D Flip-Flop (Data Flip-Flop)
Working principle
The D flip-flop stores the value present at input "D" when the active clock edge occurs.
- "D = 0" → Output becomes "0" at the rising edge.
- "D = 1" → Output becomes "1" at the rising edge.
- Between clock edges → The output retains its stored value.
Truth table
Clock event| D| Next Q
Rising edge| 0| 0
Rising edge| 1| 1
No active edge| X| Hold
Here, "X" in the no-edge row means the input may be either value; it does not mean the stored output becomes unknown.
SystemVerilog code
module dff (
input logic clk,
input logic rstn,
input logic d,
output logic q
);
always_ff @(posedge clk or negedge rstn) begin
if (!rstn)
q <= 1'b0;
else
q <= d;
end
endmodule
This implementation uses an active-low asynchronous reset. When "rstn = 0", the output is cleared without waiting for a clock edge.
Where is it used?
- Data and pipeline registers.
- State storage in FSMs.
- Synchronizer stages.
- Registering outputs to meet timing requirements.
Design tip: A chain of D flip-flops can form a shift register or a pipeline.
Explore the example in EDA Playground.
💻 Try D Flip-Flop in SystemVerilog▶ Open D Flip-Flop in EDA Playground
🔁 3. JK Flip-Flop
Working principle
The JK flip-flop is a versatile flip-flop that supports four operations.
J| K| Operation| Next Q
0| 0| Hold| Q
0| 1| Reset| 0
1| 0| Set| 1
1| 1| Toggle| ~Q
The special feature of the JK flip-flop is its toggle operation when both inputs are "1".
SystemVerilog code
module jkff (
input logic clk,
input logic rstn,
input logic j,
input logic k,
output logic q
);
always_ff @(posedge clk or negedge rstn) begin
if (!rstn)
q <= 1'b0;
else begin
case ({j, k})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= ~q;
endcase
end
end
endmodule
Practical example
Suppose the current output is "Q = 0".
If "J = 1" and "K = 1", the next rising clock edge changes "Q" to "1". If both inputs remain "1", the following rising edge changes "Q" back to "0".
The output toggles once per active clock edge.
Applications
- Counter circuits.
- Toggle-based control logic.
- Frequency-divider designs.
- Learning sequential logic behavior.
Important: A clocked JK RTL model like this represents edge-triggered behavior. It should not be confused with a level-sensitive JK latch.
Explore the example in EDA Playground.
💻 Try JK Flip-Flop in SystemVerilog▶ Open JK Flip-Flop in EDA Playground
🔄 4. T Flip-Flop (Toggle Flip-Flop)
Working principle
The T flip-flop has one control input, "T".
- "T = 0" → Hold the current output.
- "T = 1" → Toggle the output at the next rising edge.
Truth table
T| Current Q| Next Q
0| 0| 0
0| 1| 1
1| 0| 1
1| 1| 0
SystemVerilog code
module tff (
input logic clk,
input logic rstn,
input logic t,
output logic q
);
always_ff @(posedge clk or negedge rstn) begin
if (!rstn)
q <= 1'b0;
else if (t)
q <= ~q;
end
endmodule
Notice that there is no "else" assignment. In a clocked process, the flip-flop retains its previous value when "T = 0".
Practical example: Frequency division
When "T" is permanently "1", the output toggles at every rising edge. For an ideal clocked T flip-flop, the output frequency is half the input clock frequency:
Output frequency = Input clock frequency / 2
For example, a 100 MHz input clock produces a 50 MHz output, assuming the output toggles at each rising edge and the circuit operates ideally.
Applications
- Binary counters.
- Clock frequency division.
- Toggle control circuits.
- Sequential arithmetic circuits.
Explore the example in EDA Playground.
💻 Try T Flip-Flop in SystemVerilog▶ Open T Flip-Flop in EDA Playground
🧷 5. SR Flip-Flop (Set-Reset Flip-Flop)
Working principle
The SR flip-flop has two control inputs: "S" for Set and "R" for Reset.
S| R| Operation| Next Q
0| 0| Hold| Q
0| 1| Reset| 0
1| 0| Set| 1
1| 1| Forbidden for a conventional active-high SR element| Undefined by the basic model
The final row requires care. For a conventional active-high SR latch, setting both inputs to "1" is forbidden. In this clocked behavioral model, we will explicitly mark the corresponding combination as unknown to flag an invalid test condition. That is a simulation convention, not a universal physical output.
SystemVerilog code
module srff (
input logic clk,
input logic rstn,
input logic s,
input logic r,
output logic q
);
always_ff @(posedge clk or negedge rstn) begin
if (!rstn)
q <= 1'b0;
else begin
case ({s, r})
2'b00: q <= q;
2'b01: q <= 1'b0;
2'b10: q <= 1'b1;
2'b11: q <= 1'bx;
endcase
end
end
endmodule
Applications
- Set/reset control logic.
- Status and event storage.
- Understanding basic memory elements.
- Sequential circuit design education.
RTL warning: Assigning "1'bx" is useful for exposing an invalid condition in simulation, but it is not a physical logic value that hardware can generate. For synthesizable production designs, define how illegal inputs should be handled according to the design requirements.
Explore the example in EDA Playground.
💻 Try SR Flip-Flop in SystemVerilog▶ Open DSR Flip-Flop in EDA Playground
🧪 6. Testbench: How to Verify a Flip-Flop
A testbench applies inputs, generates a clock, and checks whether the output matches the expected result.
Example testbench for a D flip-flop:
module tb_dff;
logic clk;
logic rstn;
logic d;
logic q;
dff dut (
.clk (clk),
.rstn (rstn),
.d (d),
.q (q)
);
initial clk = 1'b0;
always #5 clk = ~clk;
initial begin
rstn = 1'b0;
d = 1'b0;
repeat (2) @(negedge clk);
rstn = 1'b1;
@(negedge clk);
d = 1'b1;
@(posedge clk);
#1;
assert (q === 1'b1)
else $error("DFF failed to capture 1");
@(negedge clk);
d = 1'b0;
@(posedge clk);
#1;
assert (q === 1'b0)
else $error("DFF failed to capture 0");
$display("DFF test completed");
$finish;
end
endmodule
What should you verify?
- Reset drives the output to the expected initial value.
- Data is captured at the active clock edge.
- Input changes between clock edges do not immediately change the output.
- The output holds its value when the control input requests a hold.
- All legal input combinations are tested.
Using "===" in assertions allows the testbench to detect unknown ("X") and high-impedance ("Z") values rather than silently treating them like ordinary binary values.
📊 7. Comparison of All Four Flip-Flops
Feature| D| JK| T| SR
Inputs| D| J, K| T| S, R
Hold| Not a separate input mode| J=K=0| T=0| S=R=0
Set| D=1| J=1, K=0| Not directly| S=1, R=0
Reset| D=0| J=0, K=1| Not directly| S=0, R=1
Toggle| Not directly| J=K=1| T=1| Not directly
Common use| Registers| Control and counters| Counters| Set/reset control
Explore the example in EDA Playground.
💻 Try 4 Flip-Flops in SystemVerilog▶ Open 4 Flip-Flop in EDA Playground
🏁 Conclusion
Flip-flops are fundamental building blocks of digital systems. Understanding D, JK, T, and SR flip-flops helps you design and verify registers, counters, control logic, and finite state machines.
Start by understanding the truth tables, then write the RTL, build a testbench, and verify the behavior at every clock edge.
🚀 Keep learning, keep coding, and keep building your digital design skills with Digital Electronics Guide!
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