🔄 Flip-Flops in Digital Electronics: JK, D, T, and SR Flip-Flops in SystemVerilog

📘 Introduction

Flip-flops are the building blocks of sequential digital circuits. They are bistable elements, meaning they store one bit of information (0 or 1). Flip-flops change state based on input signals and clock edges. In this blog, we will explore 4 important types of flip-flops using SystemVerilog code:

• JK Flip-Flop

• D Flip-Flop

• T Flip-Flop

• SR Flip-Flop

Each flip-flop is discussed with design code and a testbench to visualize its behavior.

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🔁 1. JK Flip-Flop

💡 Working

• J = 0, K = 0: No change

• J = 0, K = 1: Reset (Q = 0)

• J = 1, K = 0: Set (Q = 1)

• J = 1, K = 1: Toggle

🧩 SystemVerilog Code

module jk(input j, input k, input clk, output reg q);
  always @(posedge clk) begin
    case ({j, k})
      2'b00: q <= q;
      2'b01: q <= 0;
      2'b10: q <= 1;
      2'b11: q <= ~q;
    endcase
  end
endmodule

🧪 Testbench

module tb_jk;
  reg j, k, clk;
  wire q;
  jk dut(j, k, clk, q);
  initial clk = 0;
  always #5 clk = ~clk;
  initial begin
    $monitor("Time=%0t | J=%b K=%b Q=%b", $time, j, k, q);
    j = 0; k = 0;
    #10 j = 0; k = 1;
    #10 j = 1; k = 0;
    #10 j = 1; k = 1;
    #10 $finish;
  end
endmodule

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🧷 2. D Flip-Flop (Data or Delay Flip-Flop)

💡 Working

• Q follows D on the rising edge of the clock.

• It is the simplest flip-flop used for latching data.

🧩 SystemVerilog Code

module dff(input d, clk, rstn, output reg q);
  always @(posedge clk or negedge rstn)
    if (!rstn)
      q <= 0;
    else
      q <= d;
endmodule

🧪 Testbench

module tb_dff;
  reg d, clk, rstn;
  wire q;
  dff dut(.d(d), .clk(clk), .rstn(rstn), .q(q));
  initial clk = 0;
  always #5 clk = ~clk;
  initial begin
    rstn = 0; d = 0;
    #10 rstn = 1;
    #10 d = 1;
    #10 d = 0;
    #10 d = 1;
    #20 $finish;
  end
endmodule

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🔄 3. T Flip-Flop (Toggle Flip-Flop)

💡 Working

• T = 0: No change

• T = 1: Toggle output

It is commonly used in counters.

🧩 SystemVerilog Code

module tff(input t, clk, rstn, output reg q);
  always @(posedge clk or negedge rstn)
    if (!rstn)
      q <= 0;
    else if (t)
      q <= ~q;
endmodule

🧪 Testbench

module tb_tff;
reg t, clk, rstn;
wire q; tff dut(.t(t), .clk(clk), .rstn(rstn), .q(q)); initial clk = 0;
always #5 clk = ~clk; initial begin
rstn = 0; t = 0;
#10 rstn = 1;
#10 t = 1;
#50 $finish;
end
endmodule 

🧷 4. SR Flip-Flop (Set-Reset)

💡 Working

• S = 1, R = 0: Set

• S = 0, R = 1: Reset

• S = 0, R = 0: Hold

• S = 1, R = 1: Invalid (Not allowed)

🧩 SystemVerilog Code

module sr(input s, input r, input clk, output reg q);
  always @(posedge clk) begin
    case ({s, r})
      2'b00: q <= q;
      2'b01: q <= 0;
      2'b10: q <= 1;
      2'b11: q <= 1'bx; // Invalid state
    endcase
  end
endmodule

🧪 Testbench

module tb_sr;
reg s, r, clk;
wire q; sr dut(s, r, clk, q); initial clk = 0;
always #5 clk = ~clk; initial begin
$monitor("Time=%0t | S=%b R=%b Q=%b", $time, s, r, q);
s = 0; r = 0;
#10 s = 1; r = 0;
#10 s = 0; r = 1;
#10 s = 1; r = 1; // Invalid
#10 $finish;
end
endmodule 

📌 Summary Table

Flip-Flop	Inputs	Function
D	D	Q = D on clk edge
JK	J, K	Toggle / Set / Reset
T	T	Toggle when T=1
SR	S, R	Set / Reset / Invalid